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The following parameters may be specified when starting the module. These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init

Example: modprobe dwc_otg speed=1 otg_cap=1

Parameter NameMeaning

otg_cap Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified.
  • 0: HNP and SRP capable (default, if available)
  • 1: SRP Only capable
  • 2: No HNP/SRP capable

dma_enable Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified.
  • 0: Slave
  • 1: DMA (default, if available)

dma_burst_size The DMA Burst size (applicable only for External DMA Mode).
  • Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)

speed Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type.
  • 0: High Speed (default)
  • 1: Full Speed

host_support_fs_ls_low_power Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
  • 0: Don't support low power mode (default)
  • 1: Support low power mode

host_ls_low_power_phy_clk Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
  • 0: 48 MHz (default)
  • 1: 6 MHz

enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software.
  • 0: Use cC FIFO size parameters
  • 1: Allow dynamic FIFO sizing (default)

data_fifo_size Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
  • Values: 32 to 32768 (default 8192)

Note: The total FIFO memory depth in the FPGA configuration is 8192.

dev_rx_fifo_size Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
  • Values: 16 to 32768 (default 1064)

dev_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
  • Values: 16 to 32768 (default 1024)

dev_perio_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
  • Values: 4 to 768 (default 256)

host_rx_fifo_size Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
  • Values: 16 to 32768 (default 1024)

host_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled in the core.
  • Values: 16 to 32768 (default 1024)

host_perio_tx_fifo_size Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
  • Values: 16 to 32768 (default 1024)

max_transfer_size The maximum transfer size supported in bytes.
  • Values: 2047 to 65,535 (default 65,535)

max_packet_count The maximum number of packets in a transfer.
  • Values: 15 to 511 (default 511)

host_channels The number of host channel registers to use.
  • Values: 1 to 16 (default 12)

Note: The FPGA configuration supports a maximum of 12 host channels.

dev_endpoints The number of endpoints in addition to EP0 available for device mode operations.
  • Values: 1 to 15 (default 6 IN and OUT)

Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0.

phy_type Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type.
  • 0: Full Speed
  • 1: UTMI+ (default, if available)
  • 2: ULPI

phy_utmi_width Specifies the UTMI+ Data Width. This parameter is applicable for a phy_type of UTMI+. Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.
  • Values: 8 or 16 bits (default 16)

phy_ulpi_ddr Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if phy_type is ULPI.
  • 0: single data rate ULPI interface with 8 bit wide data bus (default)
  • 1: double data rate ULPI interface with 4 bit wide data bus

i2c_enable Specifies whether to use the I2C interface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS.
  • 0: Disabled (default)
  • 1: Enabled

ulpi_fs_ls Specifies whether to use ULPI FS/LS mode only.
  • 0: Disabled (default)
  • 1: Enabled

ts_dline Specifies whether term select D-Line pulsing for all PHYs is enabled.
  • 0: Disabled (default)
  • 1: Enabled

en_multiple_tx_fifo Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.
  • 0: Disabled
  • 1: Enabled (default, if available)

dev_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
  • Values: 4 to 768 (default 256)

tx_thr_length Transmit Threshold length in 32 bit double words
  • Values: 8 to 128 (default 64)

rx_thr_length Receive Threshold length in 32 bit double words
  • Values: 8 to 128 (default 64)

thr_ctl Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx transfers accordingly. The driver will automatically detect the value for this parameter if none is specified.
  • Values: 0 to 7 (default 0) Bit values indicate:
  • 0: Thresholding disabled
  • 1: Thresholding enabled

dma_desc_enable Specifies whether to enable Descriptor DMA mode. The driver will automatically detect the value for this parameter if none is specified.
  • 0: Descriptor DMA disabled
  • 1: Descriptor DMA (default, if available)

mpi_enable Specifies whether to enable MPI enhancement mode. The driver will automatically detect the value for this parameter if none is specified.
  • 0: MPI disabled (default)
  • 1: MPI enable

pti_enable Specifies whether to enable PTI enhancement support. The driver will automatically detect the value for this parameter if none is specified.
  • 0: PTI disabled (default)
  • 1: PTI enable

lpm_enable Specifies whether to enable LPM support. The driver will automatically detect the value for this parameter if none is specified.
  • 0: LPM disabled
  • 1: LPM enable (default, if available)

ic_usb_cap Specifies whether to enable IC_USB capability. The driver will automatically detect the value for this parameter if none is specified.
  • 0: IC_USB disabled (default, if available)
  • 1: IC_USB enable

ahb_thr_ratio Specifies AHB Threshold ratio.
  • Values: 0 to 3 (default 0)

power_down Specifies Power Down(Hibernation) Mode. The driver will automatically detect the value for this parameter if none is specified.
  • 0: Power Down disabled (default)
  • 2: Power Down enabled

reload_ctl Specifies whether dynamic reloading of the HFIR register is allowed during run time. The driver will automatically detect the value for this parameter if none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 the core might misbehave.
  • 0: Reload Control disabled (default)
  • 1: Reload Control enabled

dev_out_nak Specifies whether Device OUT NAK enhancement enabled or no. The driver will automatically detect the value for this parameter if none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.
  • 0: The core does not set NAK after Bulk OUT transfer complete (default)
  • 1: The core sets NAK after Bulk OUT transfer complete

cont_on_bna Specifies whether Enable Continue on BNA enabled or no. After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the
  • 0: Core starts processing from the DOEPDMA descriptor (default)
  • 1: Core starts processing from the descriptor which received the BNA. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.

ahb_single This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation.
  • 0: The remainder data will be sent using INCR burst size (default)
  • 1: The remainder data will be sent using SINGLE burst size.

adp_enable Specifies whether ADP feature is enabled. The driver will automatically detect the value for this parameter if none is specified.
  • 0: ADP feature disabled (default)
  • 1: ADP feature enabled

otg_ver Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 USB OTG device.
  • 0: OTG 2.0 support disabled (default)
  • 1: OTG 2.0 support enabled

Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  doxygen 1.3.9.1